1. Field of the Invention
The invention relates generally to logic circuits, and more specifically, to a domino circuit topology for use with low threshold voltage devices.
2. Description of Related Art
Logic systems implemented in complimentary metal oxide semiconductor (CMOS) devices are widely used in many types of computing systems. A useful semiconductor integrated logic circuit is known as "Domino," which is described in detail, for example, in a paper by R. H. Krambeck, et al. entitled "High-Speed Compact Circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, pp. 614-619 (1982).
In general, a domino circuit comprises a collection of logic gates, at least some of which deliver logic signals as logic input signals to other gates. This entire circuit is periodically activated by a single clock edge during each period. FIG. 1 illustrates a typical prior art domino circuit 10. The prior art domino circuit 10 includes a clocked positive-channel metal oxide semiconductor (PMOS) precharge transistor 12 coupled between a voltage source V.sub.cc and an evaluation network 13 that may or may not be clock gated. In a typical domino circuit, the evaluation network 13 comprises a plurality of NMOS transistors arranged to perform a given logic function. The evaluation network 13 essentially functions as a switch that may close to establish a path to V.sub.ss in response to a plurality of inputs provided thereto. In FIG. 1, the evaluation network is illustrated symbolically as a single negative-channel metal oxide semiconductor (NMOS) transistor 14 coupled to an input 15.
The NMOS evaluation transistor 14 is coupled to a common voltage rail V.sub.ss that is tied to the device substrate (indicated by a ground connection 16 on the V.sub.ss line). A CMOS stage 18 is coupled to a dynamic node 20 formed at the junction of the NMOS evaluation transistor 14 and the precharge transistor 12. The static CMOS stage 18 comprises a PMOS transistor 22 and an NMOS transistor 24 coupled in series to form an inverter. An output terminal 26 of the static CMOS stage 18 may be coupled to the input of a succeeding domino gate's evaluation network 28. Further, a "keeper" circuit 29 may to be employed to hold the state of the dynamic node 20. In FIG. 1, the keeper circuit comprises an inverter 30 and a PMOS transistor 32.
Each clock period includes a precharge phase that establishes the output terminal 26 at a predetermined logic level, and an evaluate phase, where the input terminals 15 coupled to the evaluation network 13 are evaluated. The precharge phase occurs when the clock is low. The low clock turns on the precharge transistor 12, precharging the dynamic node 20 logically high, and in turn, discharging the output 26 terminal through the NMOS transistor 24. Hence, the output 26 terminal is precharged logically low.
The evaluation phase occurs when the clock goes high. The high clock turns off the precharge transistor 12. If the input terminals 15 to the evaluation network 13 are configured such that a path to V.sub.ss is established, the logic high at the dynamic node 20 will discharge through the evaluation network 13. The evaluation network 13 is illustrated symbolically in FIG. 1 as the NMOS evaluation transistor 14. Thus, if the input terminal 15 to the NMOS evaluation transistor 14 is at a logically high level, the NMOS evaluation transistor 14 will turn on and provide a discharge path to V.sub.ss for the dynamic node 20. This will turn the NMOS transistor 24 off and turn the PMOS transistor 22 on, resulting in the output terminal 26 evaluating at logic high. If the input terminal 15 is at a logically low level, the NMOS evaluation transistor 14 remains off, and does not establish a discharge path to V.sub.ss . In this situation, the dynamic node 20 and the output terminal 26 remain at their precharge levels during the evaluation phase.
In FIG. 1, the output terminal 26 is shown coupled to the input of a succeeding domino gate's evaluation network 28. Typically, several domino gates are cascaded in this manner, so that each gate commutes its prescribed logic function during the evaluate phase that occurs once per clock period. Thus, when the circuit is clocked, each gate commutes its prescribed function, one after another, analogously to the falling of a series of dominos. Like dominos, once the dynamic node 20 "falls" (evaluates to a logic low), it stays "fallen" until it is "picked up" by the precharge phase of the next cycle.
Domino logic gates provide several advantages over static CMOS gates, including higher speed and smaller area. However, subthreshold leakage currents and noise immunity at the input terminals are concerns with known domino circuits. Further, scaling supply voltages is attractive for improving device performance and reducing overall system power requirements. While scaling threshold voltages benefits static CMOS gates, the noise immunity of domino gates is adversely affected.
As threshold voltages of circuit components are reduced, domino designs become increasingly difficult to achieve. Reduced threshold voltages result in increased leakage current, which in turn, may adversely affect power consumption. During the precharge stage, the dynamic node 20 is precharged high and the output terminal 26 is precharged low. Prior to the start of the evaluation mode, the domino logic gate 10 is in a standby mode with the dynamic node 20 and the output terminal 26 held at their precharge levels essentially by the NMOS evaluation transistor 14 and the PMOS transistor 22, respectively. The dynamic node 20 precharge level is further maintained by the keeper circuit 29. In the standby mode, static power consumption is limited to the leakage current of the NMOS evaluation transistor 14 and the PMOS transistor 22. The inverter 30 in the keeper circuit 29 is typically small and any leakage therein can be ignored. Moreover, scaling threshold voltages results in a reduced noise margin at the input of the NMOS evaluation transistor 14. This could cause the NMOS evaluation transistor 14 to switch on for smaller noise spikes at the input terminal 15, causing an unwanted discharge of the dynamic node 20.
Maintaining high threshold voltages to allow the continued use of standard domino gates may not be a viable option as this would degrade the performance of static CMOS, and prevent further reduction of supply voltages. Nevertheless, domino continues to be attractive for very high speed circuits on a chip, for example, along critical timing paths.
Thus, a need exists for a domino circuit topology that allows the use of domino circuit styles in low threshold voltage processes. The present invention addresses the above described and other shortcomings of the prior art.